An all digital phase-locked loop (ADPLL) is a digital circuit with a digitally controlled oscillator (DCO) which can be periodically adjusted so that the DCO's output phase tracks the phase (and hence, the frequency) of a reference signal.
The order of a PLL may have an effect upon the noise filtering capabilities of the PLL. For example, a type-I PLL (with a pole located at DC and due to the frequency-to-phase conversion mechanism) may be able to provide −20 dB/decade filtering of the DCO (or voltage controlled oscillator (VCO)), the reference signal, and the time-to-digital converter (TDC) phase noise. A type-II PLL (with two poles located at DC), on the other hand, may be able to provide −40 dB/decade filtering of the same under special conditions. Additionally, with respect to the DCO, type-I PLLs tend to flatten close-in 1/ω2 phase noise, while type-II PLLs have a capability to attenuate 1/ω2 phase noise by 20 dB/decade. Therefore, the use of type-II (and higher order) PLLs can be preferred due to their improved noise filtering capabilities.
However, type-II PLLs tend to have long transient settling times (when compared to type-I PLLs). The long transient settling time means that a type-II PLL will typically take longer to acquire a signal than a type-I PLL and that more time is needed for initial conditions to be eliminated from the PLL. The greater acquisition and settling times can place a limit on the frequency of the signal being tracked by the PLL.
One solution combines type-I and type-II operation and uses a type-I PLL for an initial signal acquisition phase and then switches to a type-II PLL for a signal tracking phase. The use of the type-I PLL permits a speedy lock onto the desired signal while the type-II PLL affords the noise filtering advantages of the type-II PLL.
One disadvantage of the prior art is that the use of a type-II PLL may result in slow signal acquisition and settling. This may be due in part to a type-II PLL's longer transients. The small loop bandwidth can increase the amount of time that it takes for signals to be acquired and initial conditions to settle.
A second disadvantage of the prior art is that an offset is present in the phase error from the use of the type-I PLL in the initial signal acquisition mode. This offset can increase the amount of time that the type-II PLL will require prior to being able to fully track the desired signal. This may be due to the type-II PLL's increased transients. Once again, this can have an effect on how soon the PLL is able to lock onto the desired signal.